* Question
| Which logical value states are frequently used by Verilog HDL to represent the value of the logic signal on the electrical connection line? |
* Answer
| (1)0: indicates low level, logic 0 or logic “not”; (2) 1: indicates high level, logic 1 or logic “true”; (3) X or X: uncertain or unknown logic state (4) Z or z: high impedance state; the above X and Z are not case sensitive. |
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