Ten Daily Electronic Common Sense-Section 125

What are the advantages of open-loop non-isolated flyback white LED drivers?

1. White LED current can be regulated without an external control loop.
2. Discontinuous inductive current transmission reduces EMI radiation.
3. Lower switch conduction loss.
4. Simple circuit design process.
5. The terminal voltage of the white LED can be higher or lower than the input voltage.
6. Wide input voltage range.
7. The PWM brightness adjustment signal can be easily connected.
8. The discontinuous inductor current mode of operation makes this topology suitable for low power loss applications.

What kinds of contact torque sensors are there?

1. Strain gauge torque sensor
2. Potentiometer torque sensor

What are the specific given modes given by the analog?

There are three specific ways of setting the analog quantity as follows:
One is the setting of the potentiometer: the given signal is a voltage signal, and the signal power is usually provided by the internal DC power supply (5V or 10V) of the frequency converter. The given frequency signal is obtained from the sliding contact of the potentiometer.
The second is direct voltage (or current) setting: the given signal is directly input voltage (terminal 2 and 5) or current signal (terminal 4 and 5) to the given end of the frequency converter by external devices such as sensors.
The third is auxiliary given: the inverter is equipped with auxiliary signal input terminals (terminals 1 and 5), and the auxiliary given signal is superimposed with the main given signal. It plays an auxiliary role in adjusting the output frequency of the inverter.

What are the characteristics of the storage device-SD/MMC card host controller?

Compatible with Multimedia Card (MMC) protocol version 4.0;
Compatible with SD memory card protocol version 2.0;
Compatible with SDIO memory card protocol version 1.0;
128-word buffer for sending and receiving;
Can be configured to operate based on DMA or interrupt;
3-channel SD/MMC main controller;
Support CE-ATA interface.

Brief description of the ISL6754 pin function?

• VDD: IC power supply terminal. Add a bypass capacitor to GND, and use ceramic capacitors close to VDD and GND.
• GND: IC common terminal, signal ground. One terminal is used for the power ground. Since a low-impedance layout is required for high-peak current and high-frequency operation, the ground wire should be as short as possible.
• VREF: 5V reference voltage terminal. If there is a deviation of 3%, it should be bypassed with a ceramic capacitor of 0.1-2.29F.
• CT: Oscillator timing capacitor terminal. Externally connect this end to GND, from the internal 2001. The tA current source charges, and the discharge rate is determined by the RTD terminal resistance.
• RTD: Oscillator timing capacitor discharge resistor, connected to this terminal to ground. Determine the cT current discharge range, the minimum is 20Q resistance multiplied by the resistance current. The PWM dead zone is given by the timing capacitor discharge time. RTD voltage is typically 2V.
• CS: This input is sent to the over-current comparator, and the threshold value of the over-current comparator is set to 1V. Shorting CS to ground will terminate the PWM output, depending on the sensed source impedance. The input resistor can add a delay between the internal clock and the external power switch. This delay results in CS starting to discharge before the power switch asserts.
• RAMP: This is the sawtooth wave input to the PWM comparator. The PWM signal is terminated when the RAMP terminal is shorted to ground, and a sawtooth voltage waveform is input at the upper terminal. For current-type control, this terminal is connected to cs as the feedback signal of the current loop, which is added to both inputs. For voltage-type control, the oscillator’s sawtooth wave can be buffered and used to generate a suitable signal. RAMP can be connected to the voltage feed-forward control or VREF through the ruler c network to generate the required waveform.
• OUTUL and OUTUR: They are the upper left and upper right drive signal outputs of the bridge, and they work with 50% duty cycle.
• RESDEL: Set the resonance delay period. This is the delay between the opening of the upper MOS and the lower MOS. The voltage applied to RESDEL determines the delay when the high-side MOS switch is turned on relative to the low-side MOS switch. Change the control voltage from 0 to 2V, and the resonance delay from 0 to 100%. The control voltage is divided by two existing dead times equal to the resonant delay, in practice the maximum resonant delay must be set below 2V. To ensure that the off-time of the low-side MOS is higher than that of the high-side MOS at the maximum duty cycle.
• OUTLL and OUTLR: These two outputs control the low-side MOS for pulse width modulation and switch alternately.
• OUTLLN and OUTLRN: These two are complementary signals to the PWM bridge-controlled low-side MOS drive, suitable for controlling the secondary-side synchronous rectification. The phase relationship between each output is controlled by the voltage applied to VADJ.
• VADJ: Add the control voltage from 0 to 5V to this terminal. It controls the relative delay between OUTLL and OUTLLN to ensure phase adjustment between OUTLL, OUTLR and OUTLLN, OUTLRN. At 2.425V, 0UTLLN is ahead of 0UTLL; at 2.575V, 0UTLLN lags behind OUTLL. 2. The phase difference is 0 at 5V 75mY. When internally applying a 50% voltage divider from the VREF terminal to this terminal, there is no phase delay, and this terminal is suspended externally at this time. When the phase shift is 0 or 40-300ns, the phase difference increases with the voltage, and the relationship between the control voltage and the phase difference is not linear. When the control voltage is close to 2.5V, the gain △∥△V is low, and the increase makes the voltage close to the limit of the control range. This improvement provides the user with increased control precision. When the PWM output is delayed relative to the SR output, the delay time will not exceed 90% of the dead time, which is determined by the RTD terminal and the CT terminal.
• VERR: Control voltage input terminal. It is sent to the inverting input terminal of the PWM comparator, and the output of part of the error amplifier is added to this terminal. Or directly use the optocoupler as a tight loop, and the VERR end has a 1mA pull-up current source. When VERR is driven by light or other current sources, a pull-up resistor is connected here from VREF to give a linear gain, typically a 5kΩ pull-up resistor.
• FB: The inverting input terminal of the error amplifier. The amplifier is used as an amplification of the feedback voltage, or as an average current limiting amplifier (IEA), if not used connect FB to ground.
• lOUT: Sampling and holding circuit buffer amplifier output, capture and average of CS signal.
• SS: External soft start timing capacitor. From SS terminal to GND. The soft-start capacitor value of the control IC and the internal current source determine the speed at which the duty cycle increases during startup. SS can also be used to disable the output, and a small signal transistor is connected to an open collector structure.
• CTBUF: The buffer output of the waveform at the CT end of the sawtooth oscillator. It can give a current of 2mA, which is used to set the voltage of 0.4V from GND. It has a normal peak gain of 2 which can be used for slope compensation.

Microwave RFID antenna：

Microwave RFID antennas have various structures and are the main form of IoT antennas.
It can be applied in various fields such as manufacturing, logistics, anti-counterfeiting and transportation.

What content does the web application system need to perform effective stress testing?

1. Repetition: Repetitive testing is performing an operation or function over and over again.
2. Concurrency: Execute multiple operation functions at the same time.
3. Magnitude: refers to the amount of load in each operation.
4. Random change: refers to the random change using the previous stress tests. Many different code paths are applied each test run.

Hard synchronization and resynchronization are two ways of CAN synchronization. What rules do they follow?

1. Only adapt to one mode in one bit time.
2. Only when the value detected at the previous sampling point is different from the value after a jump edge, this jump edge is used for synchronization.
3. When the bus is idle, hard synchronization is always used.
4. All transition edges suitable for ① and ② cases can be used for resynchronization. But when S is positive, the transition from recessive to dominant is not used for synchronization.

What are the technical capabilities of emergency medical terminals?

GPS positioning navigation/GIS information upload function;
Wireless transmission of audio and video monitoring data;
Vital signs remote monitoring information wireless transmission function.

Frames should be transmitted in pairs, PCD to PICC frame followed by PICC to PCD frame, what is the use sequence?

• PCD frame:
  1. PCD communication starts.
  2. Information and error detection bits transmitted by PCD as needed.
  3. PCD communication ends.
• The frame delay time from PCD to PICC.
• PICC frame:
  1. PICC communication starts.
  2. Information and error detection bits transmitted by PICC as needed.
  3. PICC communication ends.
• Frame delay time from PICC to PCD.