PIN and Block DIAGRAM
The device contains a total of 100 pins that contain different features. Although, pin connect block allows the selected pins to perform more than one function. Configuration registers command the multiplexers to allow connection between the pin and the on-chip peripherals. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled.
What is LPC1768FBD100,551?
LPC1768FBD100,551 is a 32-bit microcontroller with cost-effective Cortex-M3 core based on Ethernet, USB, CAN and 12-bit ADC and speeds up to 120MHz. It can make a CPU more flexible, adaptable and fast due to its characteristics. The maximum clock speed of the microcontroller is 100MHz and operates at temperature range of -40 °C to 85 °C.
The device has 512KB of flash memory size and 64KB of SRAM size. It has a feature of multi-layer AHB bus that offers high-bandwidth peripherals like USB and Ethernet to operate continuously with harming performance. LPC1768FBD100,551 comes in LQFP100 package.
It is pin-compatible to the 100-pin LPC236x Arm7-based microcontroller series. The Arm Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple loads and store instructions, the automatic state saves and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses.
Features
- ARM Cortex-M3 core
- Up to 120 MHz operation
- Nested Vectored Interrupt Controller for fast deterministic interrupts
- Wake-up Interrupt Controller allows automatic wake from any priority interrupt
- Memory Protection Unit
- Four reduced power modes: Sleep, Deep-sleep, Power-down and Deep power-down
- Memories
- Up to 512 KB Flash memory
- Up to 64 KB SRAM
- Serial Peripherals
- 10/100 Ethernet MAC
- USB 2.0 full-speed device/Host/ OTG controller with on-chip PHY
- Four UARTs with fractional baud rate generation, RS-485. modem control I/O, and IrDA
- Two CAN 2.0B controllers
- Three SSP/SPI controllers
- Three I2 C-bus interfaces with one supporting fast mode plus (1 Mbit/s data rates)
- I2S interface for digital audio
- Analog Peripherals
- 12-bit Analog-to-Digital Converter with eight channels
- 10-bit Digital-to-Analog Converter
- Other Peripherals
- Real-Time Clock operating at < 1 uA
- Eight-channel General-Purpose DMA controller
- Up to 70 General Purpose I/O
- Motor control PWM and Quadrature Encoder Interface to support three-phase motors
- Four 32-bit general-purpose timers/counters
- 4 MHz internal RC oscillator trimmed to 1 % accuracy
- Standard JTAG test/debug interface for compatibility with existing tools
- Four reduced power modes: sleep, deep-sleep, power-down, and deep power-down
- Brownout detect with separate threshold for interrupt and forced reset
- Unique device serial number for identification purposes
- Enhanced flash memory accelerator enables high-speed 120 MHz operations with zero wait states
- In-system programming (ISP) via on-chip boot loader software
- In-application programming (IAP) via on-chip boot loader software
- Eight-channel general-purpose DMA controller
- Split APB bus allows high throughput with few stalls between the CPU and DMA
Applications
- Entering
- Alarm systems
- Lighting
- White goods
- Industrial networking
- Motor control
- Process control
- Automotive
- Embedded design & development
- Robotics
DIMENSIONS
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