• Home
  • Parts Library
  • SSD1963QL9 Controller Introduction

    Figure 1 SSD1963QL9 module controller

    Figure 1 SSD1963QL9 module

    Figure 2 SSD1963QL9 symbol

    Figure 2 SSD1963QL9 symbol

    WAHT IS SSD1963QL9?

    SSD1963QL9 is the display controller of the 11215K byte frame buffer to support up to 864 × 480 × 24 bit graphics content. It equips parallel MCU interfaces in different bus width to receive graphics data and command from MCU. It displays interface supports common RAM-less LCD driver of color depth up to 24 bit per pixel .  The ordering part namess for SSD1963 groups are SSD1963QL9 (whose package form is TEBGA-80(Tray)), SSD1963G41 (whose package form is LQFP-128), and SSD1963QL9R (LQFP-128).


    • I/O supply power (VDDIO): 1.65V to 3.6V
    • Core supply power (VDDPLLand VDDD): 1.2V±0.1V
    • LCD interface supply power (VDDLCD): 1.65V to 3.6V
    • Deep sleep mode for power saving
    • I/O connectivity- 4 GPIO pins
    • Built-in clock generator
    • MCU connectivity – 8/916/18/24-bit MCU interface and tearing effect signal
    • Display features
    • Built-in 1215K bytes frame buffer. Support up to 864  x 480 at 24bpp display
    • Dynamic backlight control (DBC) via PWM signal
    • Programming brightness, contrast and saturation control
    • Support TFT 18/24-bit generic RGB interface panel
    • Support 8-bit serial RGB interface
    • Hardware rotation of 0, 90, 180, 270 degree
    • Hardware display mirroring
    • Hardware windowing

    SSD1963QL9 Pinout

    SSD1963QL9 Pinout

    The Pinout description is described in the SSD1963QL9 datasheet with functional block explained in the datasheet.

    SSD1963QL9 Block diagram

    SSD1963QL9 Block diagram


    Initial used: I= input, O= output, IO= Bi-directional (input/output), P= power in, Hi-Z= High impedance 

    Pin name Type Reference voltage level Description
    CS# I VDDIO Chip select
    D/C# I VDDIO Data/command select
    E(RD#) I VDDIO 6800 mode: E (enable signal)8080 mode: RD# (read strobe signal)
    R/W#(WR#) I VDDIO 6800 mode: R/W#O: write cycleI: read cycle

    8080 mode: WR# (write strobe signal)

    D[23:0] O VDDIO Data bus. Pins not used should be floating
    CONF I VDDIO MCU interface configuration0:6800 interface 1:8080 interface
    RESET# I VDDIO Master synchronize reset
    LFRAME O VDDLCD Vertical sync (frame pulse)
    LLINE O VDDLCD Horizontal sync (line pulse)
    LSHIFT O VDDLCD Pixel clock (pixel shift signal)
    LDATA[23:0] O VDDLCD RGB data
    LDEN O VDDLCD Data valid
    GPIO[3:0] IO VDDLCD These pins can be configured for display miscellaneous signals or as general purpose I/ODefault as input
    GAMAS[1:0] O VDDLCD Gamma selection for panel
    PWM O VDDLCD PWM output for backlight driver


    MCU Interface

    It connects MCU and SSD1963 graphics controller. The MCU interface can be configured as 6800 mode by the CONF pin. By pulling CONF pin VSSIO, MCU interface will be configured as 6800 mode interface. If CONF pin is connected to VDDIO, MCU interface will be configured in 8080 mode

    System clock generator

    System clock of SSD1963 is generated by built-in PLL. The reference clock of the PLL can come from either CLK pin or the external crystal oscillator. Since CLK pin and the output of the oscillator was connected to PLL with an OR gate, the unused clock must be tied to VSS.  Before the PLL output is configured as the system clock by the bit 1 of set_pll command 0xE0, the system will be clocked by the reference clock. This enables the user to send the set_pll_mn command 0xE2 to the PLL for frequency configuration. When the PLL frequency is configured and the PLL was enabled with the bit 0 of set_pll command 0xE0, the user should still wait for 100ms for the PLL to lock. And then PLL is ready and can be configured as system clock with the bit 1 of set_pll command 0xE0.

    Clock control diagram

    Figure: Clock control diagram

    Frame Buffer

    Here, there are 1215K bytes built-in SRAM inside SSD1963 to be used as frame buffer. When the frame buffer is written or read, the address counter will automatically increase by one or decrease by one depends on the frame buffer settings.

    System clock and reset manager

    This distributes the reset signal and clock signal to the entire system. It also controls clock generator and contains clock gating circuitry to turn ON and OFF the clock of each functional module. Again it divides the root clock from clock generator to operation clocks for different module. System clock and reset manager also manages reset signals to ensure all the module are reset to appropriate status when the system are in reset state, deep sleep state, sleep state and display state.

    LCD Controller

    The LCD controller has functionality to;

    • Display format where controller reads frame buffer and generates display signals according to selected display panel format
    • General purpose input/output (GPIO) where it operates in 2 modes GPIO mode and miscellaneous display signal mode. When the pins are configured as GPIOs the pins can be controlled directly by MCU. Therefore user can use these pins to emulate other interface such as SPI or I2 If these pins are configured as display signals they will toggle with display periodically according to the signal settings. They can be set to toggle once a frame once a line or in arbitrary period.


    Used as display controller
    It equips MCU interfaces to receive graphic data and commands signals


    PartsMfr.DescriptionStockPricesBuy Now
    SSD1963QL9Solomon LCD Display Controller 128-Pin LQFP Tray10560$2.946 Lowest
    SSD1961G40RSolomon LCD Display Controller3294$1.749 Lowest
    SSD1926QL9Solomon2500$3.303 Lowest
    SSD1906QT2RSolomon10$5.817 Lowest



    DISQUS: 0