
*Image from the internet; all rights belong to the original author, for reference only.
Table of Contents
ToggleSiemens Acquires Excellicon: A Systemic Reshaping of Component Selection Workflows
In May 2025, Siemens Digital Industries Software announced the acquisition of U.S.-based EDA company Excellicon, further expanding its technology footprint in timing constraint management and system-level verification. Founded in 2009, Excellicon specializes in timing modeling, constraint generation, and formal consistency checks within the chip design process. Its solutions are widely adopted in complex system-on-chip (SoC) projects, particularly in areas such as path accuracy control, power timing verification, and cross-module logic constraint management.
This acquisition marks a critical step for Siemens in its pursuit of a fully integrated EDA platform that spans from design logic to supply chain delivery. By integrating Excellicon’s technologies, Siemens aims to achieve deep interconnectivity between component selection logic, system-level path modeling, and real-time supply chain data.
This Q&A explores the implications of this acquisition, highlighting its transformative impact on electronic component selection processes and offering guidance for enterprises on how to adapt their decision-making logic in a new era.
Q1: Why Did Siemens Acquire Excellicon? What Is the Strategic Intent Behind This Move?
The acquisition of Excellicon is a strategic move to strengthen Siemens’ EDA platform capabilities and advance its ambition of delivering an end-to-end “design-verification-supply chain” solution. Excellicon is known for its expertise in modeling, verifying, and managing timing constraints—addressing key industry pain points such as inconsistent constraint rules, elusive timing issues, and frequent design iterations in complex SoC environments.
By leveraging Excellicon’s strengths in automatic SDC (synchronous design constraint) generation, formal verification, and logic integrity checks, Siemens can enhance the design closure capabilities of its existing EDA suite (including Questa, Tessent, and Aprisa). This integration will also provide a more systemic foundation for subsequent component selection, verification, and delivery processes.
Q2: How Will This Acquisition Change the Way Engineers Select Components?
Traditionally, component selection occurs in the later design stages, based on electrical parameters, compatibility, inventory, and pricing. However, as SoC complexity grows, signal integrity and timing tolerance of path-sensitive components (e.g., DDRs, PMICs, SerDes PHYs) have become critical to overall system stability.
With Excellicon’s integration, engineers can now perform comprehensive path modeling and boundary constraint generation as early as the schematic or RTL stage. This allows for earlier and more accurate assessments of component-system topology compatibility. For example:
Critical path delay balance in daisy-chained components can be verified—e.g., ensuring trace length matching for Micron MT40A512M16 DDR4 chips.
Power delivery sequencing can be validated for timing alignment—e.g., the startup timing of a Dialog DA9063 PMIC must precisely match the system controller.
Cross-domain synchronization issues between interface chips can be preemptively checked—e.g., validating channel integrity of TI DS125BR820 retimers in high-speed links.
This shifts the selection criteria towards “system-level compatibility,” moving beyond parameter-based or experience-driven choices.
Q3: What Specific Impact Will This Have on the Components Themselves?
The acquisition will directly influence how the following component categories are validated during selection:
High-speed interface chips (e.g., Analog Devices ADN4664, NXP PTN36043, TI TUSB1046): Signal integrity and path alignment can be verified at the logic design stage, reducing board-level debugging and part substitutions.
Power management ICs (PMICs) and LDOs (e.g., Renesas ISL91211, TI TPS65218, ROHM BD71837): Modeling will assist in verifying power-up sequencing and voltage stability against SoC internal boundary conditions.
Memory and controller devices (e.g., Winbond W25Q128JV, Micron MT29F4G08ABADAWP, Cypress S34ML01G2): Cross-module access paths can be simulated early to predict access conflicts.
FPGAs, MCUs, SoCs (e.g., Xilinx Zynq-7000, ST STM32H7, NXP i.MX RT1170): Their interaction with peripherals can be jointly validated for timing budget and system-level performance compliance.
These capabilities help eliminate incompatible components before they enter the production BOM, improving both selection quality and project reliability.
Q4: How Will This Transformation Affect Component Selection Efficiency and Risk Control?
As EDA tools gain better expression of path constraints, component selection workflows will see major enhancements in three areas:
Front-loaded validation reduces rework: System bottlenecks can be identified early, avoiding redesigns due to signal drift or constraint conflicts. For instance, failing to validate RTL-level timing constraints when using an Intel Cyclone 10 GX with a DDR4 controller can lead to costly PCB redesigns.
Real-time supply chain data integration: Through Siemens’ integration with Supplyframe, engineers gain access to real-time component availability, lifecycle data, and alternatives. When selecting Murata GRM capacitors, for example, it becomes possible to instantly check whether the part is approaching end-of-life.
Improved component quality in selection: Selected parts will now meet performance, timing, and supply chain stability requirements simultaneously, shortening the design-verification-production cycle.
Ultimately, organizations benefit from fewer component changes, shorter validation times, and lower project failure risks.
Q5: What New Decision-Making Logic Should Guide Component Selection in This New EDA Landscape?
As EDA platforms integrate deeper into the selection process, traditional “specs vs. cost” thinking must evolve into a more systemic approach. Three key principles should guide this transformation:
System-path compatibility trumps spec optimization: Components must be evaluated based on path modeling and architectural fit. For example, Infineon TLE92466QX as a CAN driver should be checked for timing alignment with the SPI chain of the main controller.
Timing consistency is a baseline compliance threshold: Components that fail boundary and path validation—even if spec-compliant—should be ruled out, establishing design feasibility as a selection gate.
Cross-functional collaboration in selection: With real-time supply and lifecycle forecasting from the EDA platform, procurement can intervene early to secure parts, plan substitutions, and manage supply risks—e.g., proactively flagging ON Semiconductor NCP81239 as high risk due to supply volatility.
These updated criteria reflect a shift toward system reliability and strategic agility in today’s uncertain electronics landscape.
Conclusion: From Component to System—Selection Is No Longer an Isolated Task
Siemens’ acquisition of Excellicon is more than a product line enhancement—it’s a structural leap toward a unified “component selection–logic verification–supply chain control” workflow. In this paradigm shift, component selection evolves from a static checklist into a dynamic, model-driven, and data-informed decision process.
For companies prioritizing system reliability, development efficiency, and risk mitigation, embracing this shift is essential to building next-generation competitive advantage.
© 2025 Win Source Electronics. All rights reserved. This content is protected by copyright and may not be reproduced, distributed, transmitted, cached or otherwise used, except with the prior written permission of Win Source Electronics.
COMMENTS