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  • Ultra Low Noise Push-Pull Controller – What is the LTl 683 pin function?

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    Ultra Low Noise Push-Pull Controller – What is the LTl 683 pin function?


    (1) V5 (5PIN): This terminal provides a 5V output, which can output lomA current or leakage of 10mA current.The source current comes from the VIN terminal and sinks current into GND.VIN must be greater than 6.5V, externally add lgF capacitor to reduce noise, if not open.

    (2) GND (11PIN): IC signal ground.Ground it to disable the output.Increasing this terminal voltage turns on the internal bandgap reference, giving the IC an accurate turn-on threshold.When the voltage at the SHDN terminal increases by more than 1.39V, the internal LD0 regulator is turned on to enable the control circuit.This terminal voltage can also be pulled up to ‰.

    (4) V1N (17PIN): IC power supply terminal.All supply current is supplied from this terminal, including the gate drive and the V 5 regulator, which drives the external MOSFET gate, which can be reduced to the mA stage and bypassed with a low ESR capacitor.The oscillator frequency is set close to the external clock frequency, and the clock is synchronized to the external frequency to establish a more stable switching voltage and the position of the switching current harmonics. If this terminal is not used, it can be opened.

    (7) CT (7PIN): Oscillator timing capacitor terminal.

    (9) GATEA, GATEB (1P1N, 19PIN): The gates of the external power MOSFETs at both ends, the two outputs are alternately turned on and off, and the driving capability is 300mA.

    (10) GCL (3PIN): This terminal sets the upper limit voltage of the gate drive. The gate drive terminal will not activate until 嵋N does not reach the voltage set by the GCI terminal.If this terminal is connected to a Zener or voltage source, the maximum gate drive voltage is approximately %CL to 0.2V; if it is connected to the VIN terminal, the maximum gate voltage is ziN-1.6V.From this end, 50 ̈A current can be sourced, at this time %CL<KN-0.8V.

    (11) CAPA, CAPB (2PIN, 18PIN), these two terminals are feedback nodes for external voltage rate control capacitors, usually connected to the drain of the corresponding MOSFET from 1 to 5pF.The rate of N and OFF in time will determine the d//dt when the MOSFET is switched, thereby reducing the corresponding harmonic noise.This time is proportional to R csl and R.And the maximum current, a longer time to generate a large high-frequency harmonic attenuation.l, CVAm and input voltage, the longer the time, the more harmonics are reduced.CVAm is connected to the drain of the power MOSFET from the CAPA terminal or CBPB terminal.

    (14) CS (4P1N): This terminal is the input of the current sense amplifier.It has two functions: 1 current mode controlled current sampling; 2 external MOSFET current rate control.The C and SS terminals will discharge to GND, which will quickly shut down the following cycles.

    (15) FB (9PIN): feedback terminal.This terminal is used to detect the positive voltage output. It is the inverting input of the error amplifier. The non-inverting input of the amplifier is connected to the internal 1.25V reference.This terminal is used to detect the negative output voltage, connected to the inverting input of the negative voltage feedback amplifier through the l001cQ Resistors, and the negative voltage feedback amplifier provides a gain of 0.5 to the feedback terminal.This end can be opened when not in use.If the NFB is used, it will appear 0.44V below the NFB regulation point during overvoltage protection.The voltage at the C terminal is proportional to the peak current of the switch, and its normal voltage range is 0.25 to 1.27V.Of course, the upper clamp voltage is allowed to increase with compensation during slope compensation.In the event of a short circuit fault, the VC terminal will discharge to the GND level.

    (18) SS (13PIN): SS end.When the SS voltage is below the VC clamp voltage, the VC terminal will follow the rising trajectory of the SS terminal.


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