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    What are the interrupt considerations?


    (1) Read the 00000h address unit.Do not read the 00000h address in the program.When accepting an interrupt request for a maskable interrupt, the CPU reads the interrupt information (interrupt number and interrupt request level) in the interrupt response sequence from the 00000h address.At this time, the IR bit that is accepted to be interrupted is “0”.After reset, SP (UsP, ISP) is “0000h”.Therefore, if you accept an interrupt before setting a value to the SP (USP, ISP), the program may run away.Especially when using NMl interrupts, you must set the value to the ISP at the beginning of the program.

    For l instructions starting after reset, no interrupts can be generated, including NMl interrupts.When the NMl pin is at the “L” level, it cannot be transferred to the stop mode.Because the CM10 bit of the CM1 register is fixed to “0” when the NMl pin is “L” level, the channel entering the stop mode is turned off.When the NMl pin is at the “L” level, it cannot be transferred to the standby mode.The “L” level and the “H” level width of the signal input to the NMl pin must be maintained for more than 300 ns of the CPU clock for 2 cycles.(4) Change of interrupt source.If the interrupt source is changed, the IR bit of the interrupt control register may be “1” (interrupt request).Therefore, when changing the mode of the peripheral function related to the interrupt source, polarity, and timing, the IR bit must be cleared to “0” (no interrupt request) after changing these contents.


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