* Question
Why Are Sequential Execution Statements Used in Verilog?
* Answer
Verilog is fundamentally a concurrent hardware description language: separate modules, continuous assignments, and procedural blocks can operate at the same time. However, statements placed inside a procedural block are executed sequentially so that designers can describe calculations, decision priorities, state updates, and testbench behavior in a clear and deterministic order.
Sequential execution is used inside constructs such as always, always_ff, always_comb, and initial blocks. Multiple statements can be grouped with begin and end.
Sequential Statements vs. Sequential Logic
These terms describe different concepts:
- Sequential executionmeans that statements inside one procedural block are evaluated in source-code order.
- Sequential logicrefers to hardware containing stored state, such as flip-flops, registers, and counters.
A sequentially executed procedural block can describe either combinational or clocked logic, depending on its sensitivity and assignments.
Combinational Logic
A combinational block can perform several ordered calculations:
always @(*) begin
sum = a + b;
result = sum & mask;end
Blocking assignments (=) take effect immediately within the current procedural evaluation. Therefore, the second statement uses the newly calculated value of sum. This style is commonly used for combinational logic.
Sequential ordering is also useful for expressing priority:
always @(*) begin
grant = 2’b00;
if (request_a)
grant = 2’b01;
if (request_b)
grant = 2’b10;end
Because the second condition is evaluated later, request_b has priority if both requests are active.
Clocked Logic
Clocked blocks model registers and other state-holding circuits:
always @(posedge clk) begin
state <= next_state;
count <= count + 1’b1;end
Nonblocking assignments (<=) evaluate their right-hand expressions when the clock event occurs but schedule the updates for the end of the current simulation time step. Consequently, all registers appear to update together, matching the behavior of real flip-flops.
Although these statements are written sequentially, the synthesized registers operate in parallel. Source-code order normally does not create a chain of clocked hardware when nonblocking assignments are used correctly.
Design Considerations
Designers should generally use:
- Blocking assignmentsfor combinational procedural logic
- Nonblocking assignmentsfor clocked sequential logic
- Complete assignments in combinational blocks to prevent unintended latch inference
- Separate procedural blocks for independently operating hardware
- Care when reading and writing the same variable across multiple blocks, as this can create race conditions or multiple drivers
Sequential execution statements allow Verilog to describe ordered algorithms within an event while preserving the concurrent behavior of the overall hardware design. They are therefore essential for modeling priorities, conditional operations, state transitions, register transfers, loops, and verification procedures.
