CPLDs Explained: Architecture, CPLD vs FPGA, and Sourcing Discontinued Devices

Complex Programmable Logic Devices — CPLDs — occupy a precise and still-relevant place in digital design. They are not as capable as a modern FPGA, and that is exactly the point. For a wide class of applications — glue logic, power sequencing, interface bridging, boot management — a CPLD is faster to configure, cheaper to power, and simpler to reason about than a gate-array device with millions of logic cells.

This article explains what CPLDs are, how their architecture differs from FPGAs, where each device type makes sense, and which families are currently available or have recently been discontinued. It also covers the practical supply-chain question that comes after the datasheet comparison: what to do when the CPLD your design depends on reaches end of life, and how to manage that risk before it becomes a production problem.

What Is a CPLD?

A Complex Programmable Logic Device>What Is a CPLD?able logic chip that sits architecturally between a Simple Programmable Logic Device (SPLD — such as a PAL or GAL) and a full FPGA. Its fundamental building block is the macrocell: a circuit that combines a programmable AND-OR logic array with a flip-flop, enabling both combinatorial and registered logic in the same block. Multiple macrocells are grouped into function blocks, and those blocks connect through a centralized programmable interconnect — often called a global routing pool or product-term interconnect array.

The defining characteristic that makes CPLDs different from FPGAs is that their configuration is stored in non-volatile memory — flash or EEPROM. This means the device retains its programmed logic when power is removed and begins executing that logic the instant power returns, with no configuration load step. That behavior is commonly called instant-on, and it is why CPLDs appear wherever a system needs to perform a function before any processor has booted: power rail sequencing, I/O supervision, watchdog logic, or enforcing secure boot conditions on a larger downstream device.

Logic capacity in CPLDs is measured in macrocells. Densities range from 32 macrocells in simple devices like the Microchip ATF1502AS up to a few hundred in larger traditional CPLD parts, with newer crossover families reaching the equivalent of several thousand look-up tables. They are manufactured on more mature process nodes than leading-edge FPGAs, which contributes to both their cost-effectiveness and, in some cases, their longer commercial availability.

CPLD vs FPGA: Architecture and Key Differences

The most i>CPLD vs FPGA: Architecture and Key Differences an FPGA is the granularity of the logic fabric and the routing strategy. A CPLD uses a centralized interconnect: all macrocells connect through a shared, fixed-topology routing structure, which means propagation delays between any two logic blocks are predictable and uniform. Engineers can read the timing directly from the datasheet and trust that it will hold across implementations.

An FPGA, by contrast, is built from a distributed array of Configurable Logic Blocks (CLBs) interconnected by a segmented, hierarchical routing fabric. Each CLB typically contains look-up tables (LUTs) — small truth-table memories that can implement any Boolean function of their inputs — along with flip-flops and, in modern devices, hardened DSP slices or BRAM ports. The programmable routing fabric offers enormous flexibility and scales to millions of logic elements, but it introduces variable propagation delays that require careful timing analysis and closure during implementation.

A second major difference is configuration persistence. Most FPGAs use SRAM-based configuration: the bitstream that defines the logic must be loaded from an external source at every power-up, adding a startup delay that can range from a few milliseconds to several seconds depending on bitstream size. Some FPGA families — including Altera MAX 10 and Lattice MachXO2/MachXO3 — integrate on-chip flash that provides instant-on behavior similar to a traditional CPLD, blurring the boundary between the two categories. A third key distinction is scale: even the largest CPLD families top out at tens of thousands of logic gates, while high-end FPGAs from AMD and Altera now exceed one million logic elements and integrate PCIe Gen6, CXL 3.1, hardened transceivers, and on-chip AI engines.

Side-by-Side Comparison

Side-by-Side Comparison-family:Arial,Helvetica,sans-serif;font-size:12pt;border: 1px solid #ccc;padding: 10px;text-align: left">Feature

CPLD	FPGA
Logic Structure	Macrocells (AND-OR arrays + flip-flops)	Configurable Logic Blocks (LUTs + flip-flops + DSP)
Routing	Centralized interconnect; uniform delays	Distributed, segmented routing; variable delays
Configuration Memory	Non-volatile (flash/EEPROM); retained at power-off	Typically SRAM; loaded at power-up (some families have on-chip flash)
Logic Capacity	Hundreds to ~9,400 LEs in modern families	Hundreds of thousands to 1M+ logic elements
Startup Behavior	Instant-on after power-up	Requires configuration load; startup delay
Static Power	Low (tens of mW or less, family dependent)	Higher; scales with device size and activity
Timing Predictability	Deterministic; readable directly from datasheet	Variable; requires place-and-route analysis
Embedded Resources	Limited; some families include hardened I2C/SPI, small SRAM	Rich: BRAM, DSP slices, PLLs, hardened transceivers, AI engines
Unit Cost	Low for small logic budgets	Higher, but cost-efficient for complex designs
Typical Applications	Glue logic, power sequencing, boot management, protocol bridging	AI acceleration, DSP, networking, ASIC prototyping, video processing

Timing, Power, and Performance

The centralized routing of a CPLD >Timing, Power, and Performanceys — typically in the range of 5 ns for modern families — and clock rates that comfortably reach 100 MHz for most control logic applications. Because the timing is inherent to the device’s routing topology rather than dependent on placement decisions, engineers can calculate worst-case delays before synthesis and trust that the result will match what was simulated. This makes CPLDs straightforward to certify in safety-critical applications where timing must be verifiable and documented.

FPGAs achieve faster propagation and higher clock frequencies — often 300 MHz or beyond with careful pipelining — but doing so requires running a full place-and-route implementation, analyzing timing reports, and iterating on constraints. The routing fabric introduces both the flexibility and the uncertainty. For large, performance-critical designs that benefit from that flexibility, the tradeoff is clearly worthwhile. For a 32-macrocell interface decoder that just needs to translate bus signals, the overhead is unnecessary.

On the power side, traditional CPLDs are well suited for battery-powered and low-standby-power applications. Static power draw of tens of milliwatts or less is typical, depending on the family. SRAM-based FPGAs draw more static power even before any logic is switching, and dynamic power scales with the complexity and clock rates of the active design. Modern FPGA families from Lattice (CrossLink-NX, CertusPro-NX) have significantly closed this gap, particularly for edge and embedded vision applications, but as a category, CPLDs remain more power-efficient for simple, always-on control functions.

Typical Use Cases

CPLDs are most valuable when a design >Typical Use Cases logic functions to be available immediately at power-up, or when the logic must be simple enough to audit and certify without a full FPGA toolchain. Common applications include power rail sequencing (controlling the order in which supplies come up on a multi-rail board), address decoding and chip-select generation, SPI or I2C glue between peripherals using different signal conventions, watchdog circuits, and secure boot enforcement — where the CPLD is trusted to prevent unauthorized firmware from running on a downstream processor before the system has established a secure state.

Industrial automation and automotive electronics also use CPLDs extensively for safety interlock logic, where the non-volatile, instant-on nature of the device provides assurance that the logic is active before any software has loaded. Consumer electronics designs use them for low-power I/O control in devices that need to respond to hardware events before a main processor wakes from a deep-sleep state.

FPGAs take over when the design requires capabilities that exceed the macrocell architecture: parallel data pipelines, digital signal processing, embedded processor cores, multi-gigabit serial interfaces, large state machines with deep logic cones, or any application that benefits from dynamic partial reconfiguration. AI inference at the edge, 5G baseband processing, ASIC prototyping, radar and sonar signal chains, high-speed memory controllers, and embedded vision applications are all domains where FPGA logic density and embedded hard IP — DSP blocks, transceivers, PCIe controllers — are genuinely necessary.

Current CPLD Families Worth Knowing

The CPLD landscape today is smaller than it>Current CPLD Families Worth Knowingilies remain in mainstream production:

• Lattice MachXO3: A well-established flash-based crossover family offering 640 to 9,400 LUTs and 28 to 384 I/O pins. It is widely used for board-level control, industrial interfaces, and system monitoring. Lattice’s long-lifecycle commitment makes it a practical choice for designs with extended production runs.
• Lattice MachXO2: The predecessor to MachXO3, still in active production and commonly used for bridging and I/O management. Densities run up to 6,864 LUT4s. It is a recognized migration target for teams moving off discontinued Xilinx CPLD families.
• Lattice MachXO5-NX: A newer secure-control FPGA built for higher-density board management. It extends the traditional CPLD role with up to 100K logic density, AES-256 bitstream encryption, PCIe Gen2 support, and LPDDR4 — designed for data-center hardware management and root-of-trust applications.
• Altera MAX 10: A flash-based FPGA/CPLD hybrid that integrates analog-to-digital converters, user flash memory, PLLs, and embedded multipliers. It is better understood as a small FPGA with instant-on behavior than a traditional macrocell CPLD, but it fills many of the same roles in new designs.
• Microchip ATF15xx: The most traditional macrocell CPLD still actively manufactured. The ATF1502AS (32 macrocells) and ATF1504AS (64 macrocells) are flash-based, operate at 5V, and are used for legacy PAL/GAL replacement, I/O expansion, and simple peripheral control. They remain one of the few true 5V CPLD options with an active vendor behind them.

When to Choose a CPLD and When to Choose an FPGA

The decision comes down to logic>When to Choose a CPLD and When to Choose an FPGAow much toolchain overhead is appropriate for the task. A CPLD is the right choice when the logic fits within a few hundred macrocells, the device needs to be active immediately at power-up, the design will be certified and must have predictable, documentable timing, and cost or power constraints favor a simple device. Power sequencing, boot supervisory logic, protocol translation between two well-defined buses, and safety interlocks are all natural CPLD territory.

An FPGA becomes the right choice as soon as any of those constraints no longer hold: when the logic exceeds what macrocell routing can efficiently support, when the design needs embedded BRAM, DSP multipliers, PLL-driven clock management, or high-speed serial transceivers, or when the product requires dynamic reconfiguration or ASIC-level prototyping capability. Some designs use both — a small CPLD handling power sequencing and secure boot while a larger FPGA handles the main data path — which is a legitimate and common architecture, particularly in industrial and defense applications.

Hybrid devices like the Altera MAX 10 and Lattice MachXO families sit between the two categories and are worth considering when a design needs more logic flexibility than a traditional CPLD offers but does not justify the cost or power of a mid-range FPGA. They provide instant-on operation, moderate logic density, and enough embedded resources to handle straightforward embedded processing alongside I/O management.

Discontinued CPLDs: What Changed and Why It Matters

The CPLD product landscape shifte>Discontinued CPLDs: What Changed and Why It Mattersnotice covering its XC9500XL, CoolRunner XPLA3, and CoolRunner II CPLD families, along with the Spartan-II and Spartan-3 FPGA families — all products originally developed by Xilinx and inherited when AMD acquired Xilinx in 2022. Final orders for these devices were accepted through June 29, 2024. The official notice cited declining run-rates and challenges maintaining legacy test infrastructure. With that discontinuation, AMD exited the CPLD market entirely, since no direct replacement was announced for any of the affected families.

These were not obscure parts. The CoolRunner II family, introduced around 2002, and the XC9500XL series, dating from the late 1990s, had been production staples across industrial automation, automotive electronics, consumer products, and embedded control for more than two decades. Their removal from the market created a real sourcing gap for companies running long-lifecycle products — particularly in sectors like medical devices, defense, and industrial equipment where redesigning around a new CPLD family is not a quick or cheap exercise. It requires re-certification, updated toolchain validation, layout changes, and sometimes significant HDL rework depending on how closely the original code was tied to Xilinx-specific primitives.

Altera’s MAX II family (EPM240, EPM570, EPM1270, EPM2210) dates from 2004 and is a mature line; its lifecycle status should be checked against Altera’s current product discontinuance notifications before it is designed into anything new. The Altera MAX 7000 series has been fully discontinued for years, yet it still appears in legacy designs that have been in continuous production since the mid-1990s. These long tails are not unusual: industrial and embedded designs routinely stay in production for 15 to 20 years, well beyond any semiconductor’s active support window.

Sourcing Discontinued and Obsolete CPLDs

When a CPLD family reaches end of life, procurem>Sourcing Discontinued and Obsolete CPLDslast-time buy (placing a stock order before the manufacturer’s cutoff), continued sourcing from independent distribution channels after the production window closes, and migration to a functionally equivalent modern device. Each track has legitimate uses, and experienced supply chain managers typically run all three simultaneously rather than betting on a single strategy.

Last-time buys require accurate demand forecasting across the full expected product life, which is notoriously difficult. Under-buying leaves a gap; over-buying ties up capital and creates excess inventory. For high-volume designs with well-understood consumption rates, a carefully sized last-time buy is often the cleanest solution. For lower-volume or variable-demand designs, maintaining ongoing access to independent stock is a more practical hedge.

Migration to a modern replacement is eventually the right long-term answer, but timing matters. The leading migration candidates for CoolRunner II and XC9500XL designs are the Lattice MachXO2 and MachXO3 families, which offer compatible logic density ranges, similar instant-on behavior, and active vendor support with committed long-lifecycle guarantees. For designs originally targeting 5V CPLD logic, the Microchip ATF15xx series remains one of the few directly compatible options still in production. Each migration requires validating pin compatibility, propagation delay equivalence, I/O voltage levels, package availability, and toolchain portability — especially if the original HDL used vendor-specific attributes or primitives — and final approval of any replacement device belongs to the customer’s engineering team.

For teams that cannot immediately redesign — whether because of certification constraints, budget cycles, or production continuity requirements — purchasable stock can still exist across a number of supply channels once a part is past last-time-ship, and locating it becomes a sourcing exercise rather than a catalog order. WIN SOURCE, a global independent distributor of electronic components, stocks CPLDs across current-production and hard-to-find part numbers and supports shortage sourcing, lifecycle management and alternative solutions — engaged as part of an ongoing supply-chain strategy that tracks EOL notices and monitors availability, not as a reactive measure.

Part quality is the other major variable once a part is past last-time-ship. Counterfeit CPLDs are a documented risk for high-value legacy parts with limited remaining supply, and what decides whether stock is safe to buy is how the supplier manages quality. The questions worth asking are the same whoever is quoting: which quality certifications it holds (AS9120 and ISO 9001 are the most relevant for electronic components), whether it is an ERAI member, and whether it maintains documented traceability. Verifying test documentation, requesting certificate of conformance, and understanding a supplier’s inspection process should be standard practice for any discontinued component procurement.

Organizations that completed a last-time buy and are now holding more stock than current demand requires have an excess inventory route as well. BOM-level tools such as WinLink BOM and the WinConnect API let procurement teams track availability and lifecycle risk across the entire bill of materials, not just the CPLD line items under immediate pressure.

Frequently Asked Questions

Are CPLDs still manufactured and s>Frequently Asked Questions

Arial,Helvetica,sans-serif;font-size:12pt">Yes. Lattice MachXO2, MachXO3, and MachXO5-NX are in active production with stated long-lifecycle commitments. Microchip’s ATF15xx series remains available. Altera MAX 10 fills a similar role as a flash-based programmable device with instant-on behavior. The CPLD market has contracted compared to its peak, but active production families continue to serve industrial, automotive, and embedded markets.

What are the main alternatives for discontinued CoolRunner II and XC9500XL CPLDs?

The most commonly>What are the main alternatives for discontinued CoolRunner II and XC9500XL CPLDs?r comparable logic density, flash-based instant-on operation, and active toolchain support. For 5V designs, the Microchip ATF15xx series is one of the remaining active options. Pin mapping, timing equivalence, and voltage compatibility all require verification before a migration is complete.

What is the biggest risk when sourcing discontinued CPLD parts?

Counterfeit components are the prim>What is the biggest risk when sourcing discontinued CPLD parts? supply. Working with distributors that hold AS9120 or ISO 9001 certification, maintain component traceability, and can provide test documentation significantly reduces that risk. Proactive sourcing — building a supply relationship before a shortage hits — also gives teams more time to verify parts under normal conditions rather than emergency timelines.

Can a CPLD replace an FPGA in an existing design?

Generally not without redesign. A CPLD can handle the>Can a CPLD replace an FPGA in an existing design?ple combinatorial logic, state machines, glue logic, and interface decoding — but it cannot replicate the logic capacity, embedded memory, DSP blocks, or high-speed transceivers of an FPGA. If a design was implemented in an FPGA because it needed those resources, a CPLD is not a drop-in replacement.

Conclusion

CPLDs occupy a well-defined role in digital design: small logic budgets, deterministic timing,>Conclusionstant-on operation, and low power draw. FPGAs take over when logic complexity, parallelism, embedded resources, or high-speed interfaces are required. Understanding where that boundary sits — and choosing the right device for the actual requirements rather than defaulting to the more capable part — is good engineering practice and often means a lower-cost, easier-to-certify design.

The recent wave of CPLD discontinuations, led by AMD’s withdrawal from the entire CoolRunner and XC9500XL product line in 2024, has added a third dimension to the CPLD conversation: supply chain continuity. For teams running long-lifecycle products built on these devices, the technical question of how CPLDs differ from FPGAs matters less urgently than the procurement question of how to keep production running while evaluating a migration path. Those are parallel tracks, and both require attention.

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