How to configure in the passive mode of FPGA?

* Question

How to configure in the passive mode of FPGA?

* Answer

Configuring an FPGA in passive mode refers to a method where the configuration data is provided externally to the FPGA by an external controller (e.g., microprocessor, configuration device, or host system), rather than the FPGA actively fetching it from a non-volatile memory (as in active modes).

Below is a detailed explanation of how to configure an FPGA in passive mode, especially for devices like Intel (Altera) and Xilinx FPGAs:

1. Understanding Passive Mode in FPGA Configuration

Passive configuration is host-initiated. The FPGA becomes a slave device and receives configuration data through its configuration pins. There are multiple passive modes depending on the vendor:

For Intel (Altera):

Passive Serial (PS)

Passive Parallel Synchronous (PPS)

Passive Parallel Asynchronous (PPA)

For Xilinx:

Slave Serial

Slave SelectMAP (8- or 16-bit parallel)

2. Basic Steps to Configure FPGA in Passive Mode

Step 1: Power-On Initialization

After power-up, the FPGA enters an unconfigured state.

Wait for nSTATUS (Intel) or INIT_B (Xilinx) to indicate readiness.

Step 2: Select Configuration Mode

Set mode selection pins (MSEL for Intel, M[2:0] or MODE pins for Xilinx) to specify passive mode.

These pins are typically sampled on power-up or reset.

Step 3: Provide Clock and Control Signals

Provide a configuration clock (DCLK or CCLK)—can be generated externally.

Manage control pins like nCONFIG, nSTATUS, nCE, PROG_B, and INIT_B.

Step 4: Send Configuration Bitstream

The host controller (e.g., MCU or programmer) drives the configuration data into the FPGA:

Serially (1-bit) in PS/Slave Serial.

In parallel (8-bit or 16-bit) in PPS/PPA or SelectMAP modes.

Timing and protocol adherence are crucial.

Step 5: Monitor Status Pins

Watch for:

nSTATUS / INIT_B: Signals configuration errors.

CONF_DONE / DONE: Indicates completion of configuration.

Step 6: Enable Device Operation

Upon successful configuration, the FPGA transitions to user mode and begins normal operation.

3. Hardware Requirements

Host Controller: Can be a microcontroller, CPLD, or PC.

Configuration Interface: GPIO or dedicated interface supporting bitstream transfer.

Level Shifters (if voltage domains differ).

4. Use Cases for Passive Mode

When the configuration source is non-traditional or programmable, such as:

Dynamic reconfiguration.

Remote updates from host CPU.

Systems without dedicated flash.

5. Tools and File Formats

Intel: .rbf (Raw Binary File), .sof (SRAM Object File).

Xilinx: .bit, .bin files.

Use vendor tools (Quartus, Vivado) to generate the appropriate format and configuration scheme.

Summary Table

Conclusion

Passive mode configuration gives designers flexibility by allowing an external controller to fully manage the configuration sequence. This is particularly useful for systems requiring programmability, remote updates, or dynamic configuration management. Careful attention to electrical timing, configuration files, and status signal handling is essential for successful operation.