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  • Ten Daily Electronic Common Sense-Section 98

    What are the characteristics of the GPIo of the LPC2000 series ARM?

    1. The direction of each GPIO port can be independently controlled (input/output mode);
    2. The output state (high/low level) of each GPIO port can be independently set;
    3. All GPIO ports default to Enter the state.

    Due to the characteristics of its system design, RFID technology is subject to what factors?

    Label resources are extremely limited. Because the original intention of RFID system design is to support IoT applications in a very low-cost way. Therefore, its computing power, storage space and communication bandwidth are extremely limited. For example, RFID tags are limited by low cost and usually only have about 5,000 to 10,000 logic gates. And these logic gates are mainly used to implement some of the most basic label functions, and only a few licenses are left to implement other additional functions.
    In addition, the storage resources on RFID tags are also very limited. Usually the EPC area of ​​the tag can only store 96 bits of data, and the user area can only store 1-10KB of data. In the case of extremely limited label resources, how to design and implement lightweight protocols and algorithms to improve the operating efficiency of the system. For example, reducing the scanning delay, improving the positioning accuracy, and reducing the energy consumption of the reader have become a major challenge in the design of RFID systems. 
    Real-world performance is susceptible to many factors. Some physical factors in the real transmission environment, including path loss, energy absorption, signal interference, etc., bring great unreliability to the signal transmission at the physical layer, and also have a great impact on the performance of the RFID system.
    Specifically, the key factors affecting the performance of the RFID system in the real transmission environment include:
    (a) The transmit power of the reader;
    (b) Energy absorption, path loss, multipath effects;
    (C) Signal interference;
    (d) Distribution and deployment of tags.
    How to effectively analyze the impact of the above key factors on system performance indicators (scanning range, reading rate and energy consumption). Reasonable setting of optimized parameters to reduce the negative impact of the above factors on system performance has become another major challenge in RFID system design. If the influence of the above factors can be cleverly used to design optimized protocols and algorithms. Improving the performance of the system in a way of “seeking advantages and avoiding disadvantages” will transform the above challenging problems into new research opportunities.

    What is joining the link?

    Joining the link must also be device-dependent. The device can be either a source device or a target device.
    In other words, the device can either be in a transmitting state in a joining link or in a receiving state in a joining link.
    The two states of joining the link are broadcast in advertisement messages. The advertisement message sent by the network device contains enough information to enable the new device to join the network by itself. The new device can parse out enough information from the advertisement message, and then use the information to complete the process of joining the network.

    What are the interrupt controllers?

    The processor is notified of various interrupt information and error events through the interrupt controller.
    The interrupt controller can store up to 16 interrupt events. Interrupt events are routed to the common interrupt output, the interrupt controller does not provide priority and interrupt vectoring (not compatible with 8259). 
    The interrupt controller includes the Interrupt Request Register (IRR), Interrupt Mask Register (IMR), Interrupt Register (IR) and Interrupt Response Register (IAR). 
    Interrupt events are stored in the IRR, individual events are masked through the IMR, and the interrupt input in the IRR has nothing to do with interrupt masking. The interrupt signal that is not shielded by IMR generates X/INT interrupt through network synthesis. Various interrupts can be set in the IRR when the user is debugging. The interrupts handled by the interrupt handler (except New_Prm_Data, New_DDB_Prm_Data and New_Cfg_Data) must be cleared by IAR, and can be cleared by writing l to the corresponding bit. If a new interrupt request is received in the IRR while the previously acknowledged interrupt is waiting, the interrupt is reserved. Then the processor enables the mask, which ensures that there are no previous inputs in the IRR. For safety reasons, bits in IRR must be cleared before masking is enabled.

    Why is network coding helpful for multimedia streaming?

    First, R2 using network coding allows larger segmentation than typical data blocks in PULL. Using larger segments allows for “real-time” communication of cached images with no additional overhead (or even less overhead). By enabling real-time updates to the cache image, participating peers are able to better serve each other, in stark contrast to the periodic way cache images are communicated in PULL. 
    Second, when using network coding, peers in R2 perform push rather than pull operations, which allows them to better utilize their upload bandwidth resources. What’s more, in R2, even slow overlay connections can be exploited, which is usually not possible in PULL. Taken together, all of these factors contribute to better utilization of peers’ bandwidth resources, which also results in higher playback quality and lower server bandwidth costs. 
    Third, when using network coding, R2 is significantly more robust against peer departures. Since multiple upstream peers are serving the same segment at the same time, the departure of several of them poses no threat. In contrast, data blocks lost in PULL can only be served by one upstream peer at a time, and whenever an upstream peer suddenly leaves the system, its downstream peers must find it and request the lost data block again. If this chunk is close to its deadline for playback, there is a real risk that the downstream peer will miss the deadline.

    What is an embedded controller?

    The embedded controller eliminates the need for an external PC, making the PXI chassis a complete system.
    Embedded controllers provide a wealth of standard and extended interfaces. Such as serial interface, parallel interface, USB interface, mouse, keyboard port, Ethernet interface and GPIB interface. The most direct benefit brought by abundant interfaces is to save the use of instrument expansion slots and to maximize the insertion of more instrument modules in the PXI chassis. PXI stipulates that the system slot is located at the leftmost end of the bus, and the host computer can only expand its own expansion slot to the left. It cannot be extended to the right to occupy the instrument module slot.
    The embedded controller must be placed in the system horizontal. The PXI embedded controller has the advantage of being compact and easy to maintain. Most embedded controllers are 6U in size, and some are in 3U size, occupying 1 to 4 slots. Usually built-in hard disk, display interface and some other peripheral interfaces, the CPU is Pentium processor level.

    What is resistive memory integration?

    As a member of the new type of non-volatile memory, RRAM must be able to compete with the current mainstream floating gate flash, in addition to achieving the same storage performance as flash. RRAM must take advantage of high integration density to reduce cost and gain market share. 
    It is generally believed that the integration of RRAM can be divided into two types: active array (active) and passive array (passive). In an active array, field effect transistors (MOSFETs) are used as gate transistors. A 1T1R structure is formed in series with each resistive memory cell to control the reading and writing of the memory cell, and the word line and bit line are used in the integrated array to achieve the purpose of gating the memory cell. When this active structure is used, the selection transistor unit is usually prepared first, and then the RRAM memory unit is continued to be prepared at its source or drain.
    Theoretically, in this active array, the size of the area occupied by each memory cell is mainly determined by the size of the selection transistor. The area of ​​each memory cell is 6F2 (F is the feature size). In a passive array, each memory cell is defined by upper and lower electrodes formed by intersecting word lines and bit lines. The smallest memory cell area that can be achieved in a planar structure is 4F.
    Since the passive array does not depend on the front-end process of the CMOS process, it can be stacked in multiple layers to realize a three-dimensional memory structure. The effective cell area of ​​each memory cell is only 4F2/N (N is the number of stacked layers). Therefore, from the perspective of storage array integration density. Passive crossbar is the preferred way of RRAM integration, which is also one of the advantages of RRAM compared to flash memory.

    What is the detection method for the engine coolant temperature sensor?

    Unplug the connector of the engine coolant temperature sensor, drain the cooling water, and remove the coolant temperature sensor.
    Immerse the coolant temperature sensor in a beaker filled with water and heat it with an electric heater to warm the water.
    Use a multimeter to check the electrical barrier. When the water temperature is 114 to 118 °C, the two terminals of the sensor switch should be connected.
    If the test results do not meet the above rules, it means that the coolant temperature sensor is faulty and should be repaired or replaced.

    Briefly describe the LT3825/37 pin function?

    • SG (1PIN): Secondary side synchronous rectification drive output. For the gate of the secondary side synchronous rectification MOSFET, it has strong driving ability and dynamic characteristics.
    • VCC (2PIN): IC power supply voltage supply terminal. Add a 4.7-core bypass capacitor, the highest clamp is 19.5V, with under-voltage lockout function, it starts when %c reaches 15.3V, and shuts down when it drops to 9.7V.
    • TON (3PIN): connect a resistor to GND, set the minimum on-time, and turn on the switch at the beginning of each cycle. The minimum on-time simplifies the method of isolating feedback.
    • ENDLY (4PIN): connect a resistor to set the enable delay time. The feedback amplifier is disabled during this time, which reduces voltage spikes caused by leakage inductance.
    • SYNC (5PIN): The external clock sends a signal from this end to synchronize the internal oscillator frequency. The positive edge of the pulse discharges the oscillator, making PG low and SG high, and the synchronization threshold is l. 6V.
    • SFST (6PIN): This terminal is connected to GND with a capacitor to control the upward slope of the peak primary current, and is used to control the inrush current during startup. The VC terminal voltage cannot exceed the SFST terminal voltage. With the increase of the SFST terminal voltage, the maximum voltage of the VC terminal increases accordingly, which allows a larger primary peak current. The entire % ramp-up time is about 70ms/pF capacitor. If this terminal is open, there will be no soft start function.
    • OSC (7PIN): connect a capacitor to GND, set the oscillator frequency, about l00kHzxl00/pF.
    • FB (8P1N): The feedback node input of the feedback amplifier, which usually detects the period of the flyback by dividing the voltage of the third winding. This terminal also leaks an additional current to compensate for changes in load current, which is set by the RSMP terminal.
    • VC (9PIN): This terminal is used for frequency compensation to stabilize its control loop. It is the output of the feedback amplifier and the input of the current comparator, and the frequency compensation element of the switch is usually connected from this terminal to GND. This terminal voltage is proportional to the primary peak switch current. The feedback amplifier output is disabled during the on-time of the synchronous switch.
    • UVLO (10PIN): Connect a resistor divider from the VIN end to this end. The undervoltage lockout point depends on the level of VIN. When the UVL0 end is lower than its threshold, the gate drive is disabled. But there is still normal quiescent current from VCC terminal, VCC under-voltage lockout replaces this function, so %c must be large enough to guarantee operation. The bias current at this end has a window. When the UVL0 threshold exceeds the threshold, a current is sourced. The added window is equivalent to the change multiple of the bias current. The user can control the total amount of the window and change the resistance ratio of the voltage divider. If this function is useful, connect UVL0 to VCC.
    • SENSE one (11PIN), SENSE (12PIN): These two terminals are used to measure the primary switch current. Through the detection resistor at the source of the MOS switch, the peak primary current should be sampled and added to the converter control loop, so that the Irvine is connected to this resistor to reduce noise, and once SENSE is connected to signal ground, the threshold is 98mV at maximum current. Signal blanking will occur at the minimum on-time.
    • COMP (13PIN): An external filter capacitor is used to select the load compensation function, and the load compensation reduces the influence on the parasitic resistance in the feedback detection channel. A 0.1 lamp ceramic capacitor is sufficient for this purpose, and shorting this terminal to GND is also used when compensation is not required.
    • RCMP (14PIN): Select the resistor used for load compensation, if it is not used for compensation, it can be opened.
    • PGDLY (15PIN): connect an external adjustable resistor to set the delay time from the turn-off of the synchronous rectifier drive to the turn-on of the primary gate drive.
    • PG (16PIN): The gate drive output of the primary side MOSFET, this end has a large dynamic current passing capacity.
    • GND (17PIN): This terminal is the ground terminal at the bottom of the casing, which is connected to both the signal ground and the gate drive ground, and then connected to the ground terminal of the PCB board. The PCB wiring of the ground wire must be handled carefully.

    What are the two main methods of suppressing the interference magnetic field?

    1. Large-scale shielding
    2. Gradiometer


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