Ten Daily Electronic Common Sense-Section 43

According to the identification of VLAN frames, what are the three types of ports?

1. Access port: The access port is the port on the switch used to connect the user host, and it can only connect to the access link. Only allow a unique VLAN ID to pass through this port. This VLAN ID is the same as the default VLAN ID of the port (the default VLAN ID is the VLAN configured by default when the switch leaves the factory, usually VLAN1, and each port of the switch belongs to VLAN1 by default). The Ethernet frames sent by the port to the peer device are always untagged frames.
2. Trunk port: A trunk port is a port on a switch used to connect with other switches. It can only be connected to trunk links and allows frames (with Tag tags) of multiple VLANs to pass through.
3. Hybrid port: A hybrid port is a port on a switch that can be connected to both user hosts and other switches. Hybrid ports can be connected to both access links and trunk links. The Hybrid port allows frames from multiple VLANs to pass, and can strip the tags of some VLAN frames in the direction of the outgoing port.

What is a thyristor and its classification?

Thyristor is the abbreviation of thyristor (Thyristor), which is called thyristor. It is a high-power switching semiconductor device. “SCR” means).

Thyristor has the characteristics of silicon rectifier device, can work under high voltage and high current conditions, and its working process can be controlled.

It is widely used in electronic circuits such as controllable rectification, AC voltage regulation, contactless electronic switches, inverters and frequency conversion.

• There are many classification methods for thyristors:
  1. Classification according to turn-off, turn-on and control methods Thyristors can be divided into ordinary thyristors, bidirectional thyristors, reverse conducting thyristors, gate-turn-off thyristors ( GTO), BTG thyristor, temperature-controlled thyristor and light-controlled thyristor, etc.
  2. Classification by pins and polarity Thyristors can be divided into diode thyristors, triode thyristors and quadrupole thyristors according to their pins and polarities.
  3. Classification by package form Thyristor can be divided into three types: metal package thyristor, plastic package thyristor and ceramic package thyristor according to its package form. Among them, metal-encapsulated thyristors are further divided into bolt-shaped, flat-shaped, round shell-shaped, etc.; plastic-encapsulated thyristors are divided into two types with heat sink and without heat sink.
  4. Classification according to current capacity Thyristor can be divided into three types: high-power thyristor, medium-power thyristor and low-power thyristor according to current capacity. Generally, high-power thyristors are mostly packaged in metal shells, while medium and low-power thyristors are mostly packaged in plastic or ceramic packages.
  5. Classification according to turn-off speed Thyristor can be divided into ordinary thyristor and high-frequency (fast) thyristor according to its turn-off speed.

Which stage of the 3-stage pipeline instruction is executed?

1. Instruction fetch: Load an instruction from memory;
2. Decode: Identify the instruction to be executed;
3. Execute: Process the instruction and write the result back to the register.

What are the differences between FPJA and CPLD?

See page 8, Table 1.4.

What types of electronic tags can be classified according to readable and writeability?

Read-only electronic tags, Write Once Read Only (Write Once Read Only) electronic tags, read-write electronic tags, readable and writable electronic tags realized by on-chip sensors, and readable and writable electronic tags realized by transceivers.

Technical parameters and characteristics of the Resistors：

Resistors are the most used electronic components in electronic products, accounting for about 35% of the total, while some products such as color TVs account for 50%. Therefore, the quality of resistors has an important impact on products.
Commonly used resistors are carbon film resistors, metal film resistors, metal oxide film resistors, solid resistors and wirewound resistors.

• Technical parameter:
  1. Resistance and resistance: The physical properties of conductive materials that hinder the flow of current to a certain extent. In the case of ensuring the test sensitivity, it should be noted that the test voltage should be absolutely low and the time should be as short as possible to avoid errors caused by resistance heating. And make the measured power less than 10% of the rated power.
  2. Nominal resistance and tolerance: the difference between the actual value and the nominal value.
  3. Rated power: Under normal atmospheric pressure (650-800mmhg) and rated temperature, it can work continuously for a long time and can meet the maximum power allowed by performance requirements.
  4. Rated voltage: The voltage converted from the resistance value and the power, considering the electrical breakdown, is limited by the maximum working voltage after it rises to a certain value.
  5. Maximum working voltage: The maximum continuous working voltage allowed due to the limitation of size and structure.
  6. Temperature coefficient: within a specified ambient temperature range, the amount of change in resistance when the temperature changes by 1 degree.
  7. Insulation resistance: the insulation resistance between the resistance lead and the resistance housing under normal atmospheric pressure.
  8. Noise: An irregular voltage fluctuation generated in a resistor, including thermal noise and current noise. Thermal noise is due to the irregular free movement of electrons inside the conductor, which makes the voltage at any two points of the conductor change irregularly. In non-wire wound resistors, there is also current noise. Since the current noise is proportional to the operating voltage across the resistor, the index uv/v of the current noise can be measured.
  9. Stability: The ability to maintain its initial resistance value within a specified period of time under the influence of factors such as environment and load.

What are the message frame formats?

CAN2.08 stipulates that there are two different frame formats, the difference is that the length of the identifier field is different: the frame with an 11-bit identifier is called a standard frame, and the frame containing a 29-bit identifier is an extended frame. Data frame and remote frame can use two formats of standard frame and extended frame. They are separated from the preceding frame by an interframe space.

What are the characteristics of the host interface?

Asynchronous indirect SRAM interface style interface (i80 interface); 16-bit protocol register; on-chip read and write FIFO (288 words at a time) supports indirect burst transfers; supports modem boot and enables host-controlled AP startup.

What are the positioning tracking transmission methods?

Regular return, roll call return, fixed time return.

Why is the device size smaller and not always better?

For more than 30 years, electronics engineers have believed that the main way to design smaller, faster, and less expensive electronic devices is semiconductor integration, and that lithography processes, which are moving toward finer and finer levels of integration, allow for ever-higher levels of integration. However, the current situation shows that there is a tendency for the lithography process to become more and more refined to conflict with some basic laws of physics and economics.
As we enter the sub-micron era, we are bound by some important laws of physics that will change the tradeoffs engineers make between cost and performance. For most of the 90s, analog circuit design engineers liked to follow the lithography process of digital circuits, but in the late 90s, things began to change. For lithography processes below 0.5μm, the maximum allowable supply voltage is also reduced. While this is insignificant for digital circuit design engineers, it has a huge impact on analog circuit design engineers. Reduced supply voltages make it more difficult to preserve analog signals in the presence of unavoidable noise. The size reduction of each new lithography process increases the difficulty for analog circuit design engineers. In addition, device geometries tend to be smaller and smaller, resulting in ever-increasing manufacturing costs.
With the development of the times, electronic engineers must change the way of thinking about product development. In some cases, analog and digital circuits cannot continue down the same path of ever-reducing size. To meet this challenge, engineers must carefully distribute functions among devices to optimize designs for efficiency, board area, and overall cost.
In many cases, using two chips is better than using one chip. A key design challenge is choosing the dividing line between these chips. This new design principle, called smart splitting, involves several principles: Recognizing that due to manufacturing economics or the need to drive real-world loads like coaxial or twisted-pair telephone lines, some analog applications are It is impractical at conditions lower than the current supply voltage. In these cases, smart partitioning requires the use of suitable high-voltage techniques to partition the analog functions and implement the digital functions on an optimal CMOS platform. Consider the interface bandwidth required by the candidate split design. The higher the bandwidth, the higher the power consumption and thus the higher the electromagnetic interference (EMI). Smart partitioning minimizes interface bandwidth by placing as much digital processing circuitry as possible on a separate analog chip so that high-speed data streams do not have to be transmitted off-chip.
In the best practical designs, data streaming to off-chip can be done over a serial bus, which also saves pin count. Keep in mind that the final chip cost is largely dependent on the yield of the manufactured wafers. If an analog function with extreme tolerances is integrated into a new chip design, it will reduce the final yield of the fabricated wafer. So it might make sense to separate such functionality, thus avoiding the risk of testability or downstream cost issues.
Leverage existing designs when unexpectedly low yields make application-specific integrated circuit (ASIC) designs impractical. Choose the highest level of integration available and use a Field Programmable Gate Array (FPGA) to complete the design. To investigate the external passive components required to complete the new product. To achieve a same product goal, many external passive components can be eliminated by using current mixed-signal devices that contain passive components. Smart partitioning doesn’t mean that design engineers have to go back to the ’90s design pattern of putting digital functions on one chip, analog functions on another, and memory on a third. The size of the device is not impossible to be smaller, but the smaller and smaller size of the device will limit more and more applications economically. This situation is like air transportation, we can make the plane fly faster than the sound, but for most of us it is of little value.
Considering the above principles, the design principle of smart segmentation should not be regarded as an obstacle to design progress, but should be an opportunity for design engineers to develop their creativity. Smart partitioning frees design engineers from simply configuring vendor-supplied devices to create new products. It eliminates rigid mindsets and cookie-cutter problem-solving. Companies that master dexterous segmentation will become technologically unique by leveraging their design, manufacturing and software development talents.